Various digital signal processing modules and electronic devices, especially used for communication, includes ‘analog-to-digital converters’ (ADCs) that are used to convert analog signals into a sequence of digital values (for example, 8 bit digital codes for a single level of an analog signal). There are many ways to implement ADCs, for example different types of ADCs may include flash ADCs, successive approximation register (SAR) ADCs, pipelined ADCs and the like. SAR ADCs are widely used for medium to high resolution conversions (resolution commonly ranging from 8 to 16 bits) with low power consumption characteristics. Such features make SAR ADCs ideal for a wide variety of applications, for example portable/battery-powered instruments, pen digitizers, industrial controls, and data/signal acquisition. In many scenarios, a combination of the flash SAR ADCs are also widely used to make a balance between speed and resolution, where few higher bits of the digital values are converted by flash ADC and remaining lower bits of the digital values are converted by a SAR ADC.
A typical SAR ADC of the flash SAR ADC includes a sample and hold (S/H) circuit to acquire and hold analog input voltage and to ensure that the analog input voltage that is acquired, remains constant during conversion. A capacitor digital-to-analog converter (DAC) is included in the SAR ADC to supply the analog input voltage to a comparator. The comparator compares input voltage received from the S/H circuit and input voltage received from the capacitor DAC and stores a result of comparison in a SAR. The comparator determines whether the analog input voltage obtained from the capacitor DAC is higher or lower than the analog input voltage received from the S/H circuit. The SAR provides the capacitor DAC with an approximation of a digital code, such that the output of the capacitor DAC provided to the comparator is an approximation of the analog input voltage. For example, the SAR ADC employs a binary search algorithm in a feedback loop for approximately determining digital values for the analog input voltage. The approximation is improved using a result of a previous comparison and the process is repeated until an entire digital word is decoded. However, high resolution requirement of the SAR ADC reduces speed of the SAR ADC. The SAR ADC are designed with different circuit configurations for increasing the speed, however such circuit configurations do not improve performance of the SAR ADC. Such configurations also fail to reduce unnecessary variation in switching current in the capacitor DAC caused by changes in signal levels of the analog input. As variation in the current drawn from a reference voltage source is more, it can deteriorate non-linearity (INL) performance of the SAR ADC.